<?xml version="1.0" encoding="utf-8"?> <feed xmlns:dc="http://dublincore.org/documents/dcmi-namespace/" xmlns:media="http://search.yahoo.com/mrss/" xmlns="http://www.w3.org/2005/Atom"> <title type="text">Verific Design Automation</title> <subtitle type="text">Contains the last 20 releases</subtitle> <id>uuid:285810c7-76d7-43a7-b1fe-06f5013135b0;id=18141</id> <rights type="text">Copyright 2024, Verific Design Automation</rights> <updated>2024-06-19T15:00:00Z</updated> <author> <name>newsdesk@globenewswire.com (NewsDesk)</name> <uri>http://www.globenewswire.com/LegacyRss?Length=4</uri> <email>newsdesk@globenewswire.com</email> </author> <link rel="alternate" href="https://www.globenewswire.com/atomfeed/organization/RduT_dhV9HjUdW7FP3-iDQ==" /> <link rel="self" href="https://www.globenewswire.com/atomfeed/organization/RduT_dhV9HjUdW7FP3-iDQ==" /> <entry> <id>https://www.globenewswire.com/news-release/2024/06/19/2901206/0/en/Verific-s-Front-End-Platforms-Now-Powering-AI-EDA-Startups-Serving-as-Foundational-Technology-for-a-New-and-Emerging-Market.html</id> <title type="text">Verific’s Front-End Platforms Now Powering AI EDA Startups, Serving as Foundational Technology for a New and Emerging Market</title> <published>2024-06-19T15:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2024/06/19/2901206/0/en/Verific-s-Front-End-Platforms-Now-Powering-AI-EDA-Startups-Serving-as-Foundational-Technology-for-a-New-and-Emerging-Market.html" /> <content type="html"><![CDATA[Verific affirmed its position as the leading provider of front-end platforms powering an emerging EDA space, AI EDA]]></content> <dc:identifier>2901206</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Wed, 19 Jun 2024 15:00 GMT</dc:modified> <dc:subject>Calendar of Events</dc:subject> </entry> <entry> <id>https://www.globenewswire.com/news-release/2023/05/02/2659499/0/en/Verific-Confirms-Vorak-as-its-Vendor-of-Choice-for-Providing-Custom-Development-Services-to-Verific-s-Customer-Base.html</id> <title type="text">Verific Confirms Vorak as its Vendor of Choice for Providing Custom Development Services to Verific’s Customer Base</title> <published>2023-05-02T15:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2023/05/02/2659499/0/en/Verific-Confirms-Vorak-as-its-Vendor-of-Choice-for-Providing-Custom-Development-Services-to-Verific-s-Customer-Base.html" /> <content type="html"><![CDATA[Vorak’s Verific Parser Platform Knowledge and Engineering Assist Verific Customers <pre>Vorak’s Verific Parser Platform Knowledge and Engineering Assist Verific Customers</pre>]]></content> <dc:identifier>2659499</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Tue, 02 May 2023 15:00 GMT</dc:modified> <dc:subject>Product / Services Announcement</dc:subject> </entry> <entry> <id>https://www.globenewswire.com/news-release/2022/08/24/2503976/0/en/Verific-s-Rick-Carlson-Appointed-Advisory-Board-Member-for-the-College-of-Computing-at-Illinois-Institute-of-Technology.html</id> <title type="text">Verific’s Rick Carlson Appointed Advisory Board Member for the College of Computing at Illinois Institute of Technology</title> <published>2022-08-24T15:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2022/08/24/2503976/0/en/Verific-s-Rick-Carlson-Appointed-Advisory-Board-Member-for-the-College-of-Computing-at-Illinois-Institute-of-Technology.html" /> <content type="html"><![CDATA[Illinois Tech Alumnus Will Serve as Advocate to Reinforce College’s Position as Leading Creator of Computation Talent in Chicago and Beyond <pre>Illinois Tech Alumnus Will Serve as Advocate to Reinforce College’s Position as Leading Creator of Computation Talent in Chicago and Beyond</pre>]]></content> <dc:identifier>2503976</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Wed, 24 Aug 2022 15:00 GMT</dc:modified> <dc:subject>Directors and Officers</dc:subject> </entry> <entry> <id>https://www.globenewswire.com/news-release/2022/02/15/2385514/0/en/Rapid-Silicon-Chooses-Verific-s-Industry-Standard-Parser-Platform.html</id> <title type="text">Rapid Silicon Chooses Verific’s Industry-Standard Parser Platform</title> <published>2022-02-15T16:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2022/02/15/2385514/0/en/Rapid-Silicon-Chooses-Verific-s-Industry-Standard-Parser-Platform.html" /> <content type="html"><![CDATA[Parser Platform to Serve as Front End to Rapid Silicon’s Integrated Design Environment <pre>Parser Platform to Serve as Front End to Rapid Silicon’s Integrated Design Environment</pre>]]></content> <dc:identifier>2385514</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Tue, 15 Feb 2022 16:00 GMT</dc:modified> <dc:subject>Licensing Agreements</dc:subject> </entry> <entry> <id>https://www.globenewswire.com/news-release/2020/12/16/2146390/0/en/Verific-and-DARPA-Sign-Partnership-for-Streamlined-Access-to-Industry-Standard-SystemVerilog-EDA-Software.html</id> <title type="text">Verific and DARPA Sign Partnership for Streamlined Access to Industry-Standard SystemVerilog EDA Software</title> <published>2020-12-16T16:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2020/12/16/2146390/0/en/Verific-and-DARPA-Sign-Partnership-for-Streamlined-Access-to-Industry-Standard-SystemVerilog-EDA-Software.html" /> <content type="html"><![CDATA[DARPA Program Equips Community with Best-in-Class Technologies, U.S. Innovation <pre>DARPA Program Equips Community with Best-in-Class Technologies, U.S. Innovation</pre>]]></content> <dc:identifier>2146390</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Wed, 16 Dec 2020 16:00 GMT</dc:modified> <dc:subject>Partnerships</dc:subject> </entry> <entry> <id>https://www.globenewswire.com/news-release/2020/03/10/1998130/0/en/Verific-Celebrates-20-Years-of-Exceptional-Support-with-Tributes-from-Customers.html</id> <title type="text">Verific Celebrates 20 Years of Exceptional Support with Tributes from Customers</title> <published>2020-03-10T14:30:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2020/03/10/1998130/0/en/Verific-Celebrates-20-Years-of-Exceptional-Support-with-Tributes-from-Customers.html" /> <content type="html"><![CDATA[Six Short Interviews with Some of Verific's Long-Time Customers Highlight Positive Experience <pre>Six Short Interviews with Some of Verific's Long-Time Customers Highlight Positive Experience</pre>]]></content> <dc:identifier>1998130</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Tue, 10 Mar 2020 14:30 GMT</dc:modified> <dc:subject>Company Announcement</dc:subject> </entry> <entry> <id>https://www.globenewswire.com/news-release/2019/12/03/1955713/0/en/vSync-Circuits-Adds-Verific-s-Static-Elaborator-to-Product-Mix.html</id> <title type="text">vSync Circuits Adds Verific’s Static Elaborator to Product Mix</title> <published>2019-12-03T16:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2019/12/03/1955713/0/en/vSync-Circuits-Adds-Verific-s-Static-Elaborator-to-Product-Mix.html" /> <content type="html"><![CDATA[Verilog Parser Serves as Front End to New vLinter Rule-Based Design Analysis, Verification Software <pre>Verilog Parser Serves as Front End to New vLinter Rule-Based Design Analysis, Verification Software</pre>]]></content> <dc:identifier>1955713</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Tue, 03 Dec 2019 16:00 GMT</dc:modified> <dc:subject>Company Announcement</dc:subject> </entry> <entry> <id>https://www.globenewswire.com/news-release/2018/10/10/1619429/0/en/Innergy-Systems-Powers-Up-with-Verific-s-Parser-Platform.html</id> <title type="text">Innergy Systems Powers Up with Verific’s Parser Platform</title> <published>2018-10-10T15:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2018/10/10/1619429/0/en/Innergy-Systems-Powers-Up-with-Verific-s-Parser-Platform.html" /> <content type="html"><![CDATA[SystemVerilog Parser Serves as Front End to Innergy Systems’ Integrated Power Analysis Platform <pre>SystemVerilog Parser Serves as Front End to Innergy Systems’ Integrated Power Analysis Platform</pre>]]></content> <dc:identifier>1619429</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Wed, 10 Oct 2018 15:00 GMT</dc:modified> <dc:subject>Company Announcement</dc:subject> </entry> <entry> <id>https://www.globenewswire.com/news-release/2018/06/13/1521241/0/en/Verific-s-Parser-Platform-License-Secured-by-Empyrean.html</id> <title type="text">Verific’s Parser Platform License Secured by Empyrean</title> <published>2018-06-13T16:54:34Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2018/06/13/1521241/0/en/Verific-s-Parser-Platform-License-Secured-by-Empyrean.html" /> <content type="html"><![CDATA[Verilog Parser Functions as Front End to Empyrean’s Library Quality Inspection Software Qualib <pre>Verilog Parser Functions as Front End to Empyrean’s Library Quality Inspection Software Qualib</pre>]]></content> <dc:identifier>1521241</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Wed, 13 Jun 2018 16:54 GMT</dc:modified> <dc:subject>Company Announcement</dc:subject> </entry> <entry> <id>https://www.globenewswire.com/news-release/2018/05/30/1514079/0/en/Verific-Integrates-INVIO-with-Flagship-Parser-Platform.html</id> <title type="text">Verific Integrates INVIO with Flagship Parser Platform</title> <published>2018-05-30T15:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2018/05/30/1514079/0/en/Verific-Integrates-INVIO-with-Flagship-Parser-Platform.html" /> <content type="html"><![CDATA[Integration Enables Users to Simplify, Streamline Design Environment <pre>Integration Enables Users to Simplify, Streamline Design Environment</pre>]]></content> <dc:identifier>1514079</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Wed, 30 May 2018 15:00 GMT</dc:modified> <media:content medium="image" type="image/png" width="600" url="https://resource.globenewswire.com/Resource/Download/10d55175-4c9e-4c2a-8f03-340e4f493dbe"> <media:text type="html"><![CDATA[<p> <a href="https://www.globenewswire.com/news-release/2018/05/30/1514079/0/en/Verific-Integrates-INVIO-with-Flagship-Parser-Platform.html"> <img src="https://resource.globenewswire.com/Resource/Download/10d55175-4c9e-4c2a-8f03-340e4f493dbe" width="600" align="left" border="0" alt="INVIOflowchart-1" title="The INVIO platform integration with the Verific parser platform simplifies and streamlines the design environment." /> </a> </p><br clear="all" />]]></media:text> <media:credit role="publishing company">GlobeNewswire Inc.</media:credit> </media:content> <dc:subject>Company Announcement</dc:subject> </entry> <entry> <id>https://www.globenewswire.com/news-release/2017/10/11/1215498/0/en/Verific-s-Parser-Platform-Selected-as-Efinix-Integrated-Design-Environment-Front-End.html</id> <title type="text">Verific's Parser Platform Selected as Efinix Integrated Design Environment Front End </title> <published>2017-10-11T15:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2017/10/11/1215498/0/en/Verific-s-Parser-Platform-Selected-as-Efinix-Integrated-Design-Environment-Front-End.html" /> <content type="html"><![CDATA[<p><em><p>Programmable Product Platform, Technology Innovator Verific Customer Since 2014</p></em></p><p>ALAMEDA, CA--(Marketwired - Oct 11, 2017) - <strong> </strong><a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation</a> today announced <a rel="nofollow" href="http://www.efinixinc.com/" title="Efinix">Efinix</a>™, an innovator in programmable product platforms and technology, selected its Verilog Parser Platform and register transfer level (RTL) elaborator to serve as the front end to the Efinity™ Integrated Design Environment (IDE).</p>]]></content> <dc:identifier>1215498</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Fri, 01 Dec 2017 01:53 GMT</dc:modified> </entry> <entry> <id>https://www.globenewswire.com/news-release/2017/09/26/1215495/0/en/Baum-Licenses-Verific-s-Parser-Platforms.html</id> <title type="text">Baum Licenses Verific's Parser Platforms </title> <published>2017-09-26T15:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2017/09/26/1215495/0/en/Baum-Licenses-Verific-s-Parser-Platforms.html" /> <content type="html"><![CDATA[<p><em><p>SystemVerilog, Verilog Parsers Function as PowerBaum Power Analysis' Front End</p></em></p><p>ALAMEDA, CA--(Marketwired - Sep 26, 2017) - <a rel="nofollow" href="http://www.baum-ds.com/" title="Baum">Baum</a>, a leader in power analysis solutions, today became the newest licensee of <a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation</a>, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry.</p>]]></content> <dc:identifier>1215495</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Fri, 01 Dec 2017 01:53 GMT</dc:modified> </entry> <entry> <id>https://www.globenewswire.com/news-release/2017/06/12/1215492/0/en/Verific-Acquires-INVIO-Platform-from-Invionics-Software.html</id> <title type="text">Verific Acquires INVIO Platform from Invionics Software </title> <published>2017-06-12T15:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2017/06/12/1215492/0/en/Verific-Acquires-INVIO-Platform-from-Invionics-Software.html" /> <content type="html"><![CDATA[<p><em><p>Rapid Application Development Platform will be added to Verific's Parser Platform</p></em></p><p>ALAMEDA, CA--(Marketwired - Jun 12, 2017) - <a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation</a>, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry, today announced it acquired the INVIO product line from <a rel="nofollow" href="http://www.invionics.com/" title="Invionics Software">Invionics Software</a>. </p>]]></content> <dc:identifier>1215492</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Fri, 01 Dec 2017 01:53 GMT</dc:modified> </entry> <entry> <id>https://www.globenewswire.com/news-release/2017/05/23/1215487/0/en/Verific-Signs-Licensing-Agreement-with-Functional-Safety-Solutions-Provider-Austemper-Design-Systems.html</id> <title type="text">Verific Signs Licensing Agreement with Functional Safety Solutions Provider Austemper Design Systems </title> <published>2017-05-23T15:15:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2017/05/23/1215487/0/en/Verific-Signs-Licensing-Agreement-with-Functional-Safety-Solutions-Provider-Austemper-Design-Systems.html" /> <content type="html"><![CDATA[<p><em><p>Parser Platform Serves as Front End to Austemper's Functional Safety Tool Suite</p></em></p><p>ALAMEDA, CA--(Marketwired - May 23, 2017) - <a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation</a>, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry, announced a licensing agreement with <a rel="nofollow" href="http://www.austemperdesign.com/" title="Austemper Design Systems">Austemper Design Systems</a>, provider of an end-to-end functional safety solution.</p>]]></content> <dc:identifier>1215487</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Fri, 01 Dec 2017 01:53 GMT</dc:modified> </entry> <entry> <id>https://www.globenewswire.com/news-release/2017/05/16/1215486/0/en/Verific-Adds-UPF-Elaborator-to-Comprehensive-Parser-Platform-Portfolio.html</id> <title type="text">Verific Adds UPF Elaborator to Comprehensive Parser Platform Portfolio </title> <published>2017-05-16T15:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2017/05/16/1215486/0/en/Verific-Adds-UPF-Elaborator-to-Comprehensive-Parser-Platform-Portfolio.html" /> <content type="html"><![CDATA[<p><em><p>New Functionality Broadens UPF Parser/Analyzer Capabilities</p></em></p><p>ALAMEDA, CA--(Marketwired - May 16, 2017) - <a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation</a>, the recognized leader of SystemVerilog, VHDL and Unified Power Format (UPF) Parser Platforms in production and development use throughout the semiconductor industry, today announced availability of its UPF Elaborator.</p>]]></content> <dc:identifier>1215486</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Fri, 01 Dec 2017 01:53 GMT</dc:modified> </entry> <entry> <id>https://www.globenewswire.com/news-release/2017/04/12/1215484/0/en/Robert-M-Gardner-Verific-Design-Automation-and-Missing-Link-Electronics-Board-Member-Former-EDA-Consortium-Executive-Director-Dead-at-74.html</id> <title type="text">Robert M. Gardner, Verific Design Automation and Missing Link Electronics Board Member, Former EDA Consortium Executive Director, Dead at 74 </title> <published>2017-04-12T23:36:12Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2017/04/12/1215484/0/en/Robert-M-Gardner-Verific-Design-Automation-and-Missing-Link-Electronics-Board-Member-Former-EDA-Consortium-Executive-Director-Dead-at-74.html" /> <content type="html"><![CDATA[<p>ALAMEDA, CA--(Marketwired - Apr 12, 2017) - Robert M. Gardner, a resident of San Jose, Calif., died April 11 at the age of 74 after a short illness.</p>]]></content> <dc:identifier>1215484</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Fri, 01 Dec 2017 01:53 GMT</dc:modified> <media:content medium="image" type="image/jpeg" width="600" url="http://media.marketwire.com/attachments/201704/78728_Bob_Gardner_obit1.jpg"> <media:text type="html"><![CDATA[<p> <a href="https://www.globenewswire.com/news-release/2017/04/12/1215484/0/en/Robert-M-Gardner-Verific-Design-Automation-and-Missing-Link-Electronics-Board-Member-Former-EDA-Consortium-Executive-Director-Dead-at-74.html"> <img src="http://media.marketwire.com/attachments/201704/78728_Bob_Gardner_obit1.jpg" width="600" align="left" border="0" alt="Photo" title="Robert M. Gardner" /> </a> </p><br clear="all" />]]></media:text> <media:credit role="publishing company">GlobeNewswire Inc.</media:credit> </media:content> </entry> <entry> <id>https://www.globenewswire.com/news-release/2016/05/24/1215482/0/en/Verific-to-Showcase-Three-Design-Automation-Startups-With-Safety-Features-Insertion-Low-Power-Hardware-Security-Analysis-Offerings-in-Its-DAC-Booth.html</id> <title type="text">Verific to Showcase Three Design Automation Startups With Safety-Features Insertion, Low-Power, Hardware Security Analysis Offerings in Its DAC Booth </title> <published>2016-05-24T15:30:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2016/05/24/1215482/0/en/Verific-to-Showcase-Three-Design-Automation-Startups-With-Safety-Features-Insertion-Low-Power-Hardware-Security-Analysis-Offerings-in-Its-DAC-Booth.html" /> <content type="html"><![CDATA[<p><em><p>Reinforces Verific's Innovative Business Model to Jumpstart Design Automation Entrepreneurial Efforts</p></em></p><p>ALAMEDA, CA--(Marketwired - May 24, 2016) - <a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation</a>, the recognized leader of SystemVerilog, VHDL and UPF parsers, will showcase startup ventures Austemper Design, Innergy Systems and Tortuga Logic in its booth (#538) during the Design Automation Conference (DAC) June 5-9 in Austin, Texas.</p>]]></content> <dc:identifier>1215482</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Fri, 01 Dec 2017 01:53 GMT</dc:modified> </entry> <entry> <id>https://www.globenewswire.com/news-release/2016/05/12/1215480/0/en/Two-More-Verific-Licensees-Achieve-Successful-Exits.html</id> <title type="text">Two More Verific Licensees Achieve Successful Exits </title> <published>2016-05-12T15:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2016/05/12/1215480/0/en/Two-More-Verific-Licensees-Achieve-Successful-Exits.html" /> <content type="html"><![CDATA[<p><em><p>Longtime Customers Yogitech, Rocketick Acquired by Intel, Cadence, Respectively</p></em></p><p>ALAMEDA, CA--(Marketwired - May 12, 2016) - <a rel="nofollow" href="http://www.verific.com" title="Verific Design Automation">Verific Design Automation</a>, the recognized leader of SystemVerilog, VHDL and UPF parsers, today announced that two of its longtime customers joined a growing list of other customers who have achieved successful exits through acquisitions.</p>]]></content> <dc:identifier>1215480</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Fri, 01 Dec 2017 01:53 GMT</dc:modified> </entry> <entry> <id>https://www.globenewswire.com/news-release/2016/04/19/1215478/0/en/Longtime-Verific-Customer-S2C-Upgrades-to-SystemVerilog.html</id> <title type="text">Longtime Verific Customer S2C Upgrades to SystemVerilog </title> <published>2016-04-19T15:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2016/04/19/1215478/0/en/Longtime-Verific-Customer-S2C-Upgrades-to-SystemVerilog.html" /> <content type="html"><![CDATA[<p><em><p>SystemVerilog Parser Integrated with Prodigy Prototyping Platform</p></em></p><p>ALAMEDA, CA--(Marketwired - Apr 19, 2016) - <a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation</a>, the recognized leader of SystemVerilog, VHDL and UPF parsers used throughout the semiconductor industry, announced today <a rel="nofollow" href="http://www.s2cinc.com/" title="S2C, Inc.">S2C, Inc.</a>, a leading provider of FPGA-based rapid prototyping solutions, licensed its SystemVerilog parser.</p>]]></content> <dc:identifier>1215478</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific Design Automation</dc:contributor> <dc:modified>Fri, 01 Dec 2017 01:53 GMT</dc:modified> </entry> <entry> <id>https://www.globenewswire.com/news-release/2016/03/09/1215476/0/en/Verific-Design-Automation-s-Board-Member-Honored-With-DATE-Fellow-Award.html</id> <title type="text">Verific Design Automation's Board Member Honored With DATE Fellow Award </title> <published>2016-03-09T15:00:00Z</published> <updated>2024-11-26T04:01:40Z</updated> <link rel="alternate" href="https://www.globenewswire.com/news-release/2016/03/09/1215476/0/en/Verific-Design-Automation-s-Board-Member-Honored-With-DATE-Fellow-Award.html" /> <content type="html"><![CDATA[<p><em><p>Yearly Award to Be Presented to Robert Gardner During DATE's Opening Ceremonies</p></em></p><p>ALAMEDA, CA--(Marketwired - Mar 9, 2016) - <strong> </strong>Robert Gardner, longtime member of the <a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation </a>Board of Directors, will be presented with the yearly DATE Fellow Award by the Design, Automation and Test in Europe (DATE) Conference and Exhibit 2016. </p>]]></content> <dc:identifier>1215476</dc:identifier> <dc:language>en</dc:language> <dc:publisher>GlobeNewswire Inc.</dc:publisher> <dc:contributor>Verific</dc:contributor> <dc:modified>Fri, 01 Dec 2017 01:53 GMT</dc:modified> </entry> </feed>