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    <copyright>Copyright 2024, Verific Design Automation</copyright>
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      <title>Verific’s Front-End Platforms Now Powering AI EDA Startups, Serving as Foundational Technology for a New and Emerging Market</title>
      <description><![CDATA[Verific affirmed its position as the leading provider of front-end platforms powering an emerging EDA space, AI EDA]]></description>
      <pubDate>Wed, 19 Jun 2024 15:00 GMT</pubDate>
      <dc:identifier>2901206</dc:identifier>
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      <dc:modified>Wed, 19 Jun 2024 15:00 GMT</dc:modified>
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      <link>https://www.globenewswire.com/news-release/2023/05/02/2659499/0/en/Verific-Confirms-Vorak-as-its-Vendor-of-Choice-for-Providing-Custom-Development-Services-to-Verific-s-Customer-Base.html</link>
      <title>Verific Confirms Vorak as its Vendor of Choice for Providing Custom Development Services to Verific’s Customer Base</title>
      <description><![CDATA[Vorak’s Verific Parser Platform Knowledge and Engineering Assist Verific Customers <pre>Vorak’s Verific Parser Platform Knowledge and Engineering Assist Verific Customers</pre>]]></description>
      <pubDate>Tue, 02 May 2023 15:00 GMT</pubDate>
      <dc:identifier>2659499</dc:identifier>
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      <dc:modified>Tue, 02 May 2023 15:00 GMT</dc:modified>
      <dc:subject>Product / Services Announcement</dc:subject>
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      <link>https://www.globenewswire.com/news-release/2022/08/24/2503976/0/en/Verific-s-Rick-Carlson-Appointed-Advisory-Board-Member-for-the-College-of-Computing-at-Illinois-Institute-of-Technology.html</link>
      <title>Verific’s Rick Carlson Appointed Advisory Board Member for the College of Computing at Illinois Institute of Technology</title>
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      <pubDate>Wed, 24 Aug 2022 15:00 GMT</pubDate>
      <dc:identifier>2503976</dc:identifier>
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      <dc:modified>Wed, 24 Aug 2022 15:00 GMT</dc:modified>
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      <title>Rapid Silicon Chooses Verific’s Industry-Standard Parser Platform</title>
      <description><![CDATA[Parser Platform to Serve as Front End to Rapid Silicon’s Integrated Design Environment <pre>Parser Platform to Serve as Front End to Rapid Silicon’s Integrated Design Environment</pre>]]></description>
      <pubDate>Tue, 15 Feb 2022 16:00 GMT</pubDate>
      <dc:identifier>2385514</dc:identifier>
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      <dc:modified>Tue, 15 Feb 2022 16:00 GMT</dc:modified>
      <dc:subject>Licensing Agreements</dc:subject>
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      <link>https://www.globenewswire.com/news-release/2020/12/16/2146390/0/en/Verific-and-DARPA-Sign-Partnership-for-Streamlined-Access-to-Industry-Standard-SystemVerilog-EDA-Software.html</link>
      <title>Verific and DARPA Sign Partnership for  Streamlined Access to Industry-Standard SystemVerilog EDA Software</title>
      <description><![CDATA[DARPA Program Equips Community with Best-in-Class Technologies, U.S. Innovation <pre>DARPA Program Equips Community with Best-in-Class Technologies, U.S. Innovation</pre>]]></description>
      <pubDate>Wed, 16 Dec 2020 16:00 GMT</pubDate>
      <dc:identifier>2146390</dc:identifier>
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      <dc:publisher>GlobeNewswire Inc.</dc:publisher>
      <dc:contributor>Verific Design Automation</dc:contributor>
      <dc:modified>Wed, 16 Dec 2020 16:00 GMT</dc:modified>
      <dc:subject>Partnerships</dc:subject>
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      <title>Verific Celebrates 20 Years of Exceptional Support with Tributes from Customers</title>
      <description><![CDATA[Six Short Interviews with Some of Verific's Long-Time Customers Highlight Positive Experience <pre>Six Short Interviews with Some of Verific's Long-Time Customers Highlight Positive Experience</pre>]]></description>
      <pubDate>Tue, 10 Mar 2020 14:30 GMT</pubDate>
      <dc:identifier>1998130</dc:identifier>
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      <dc:subject>Company Announcement</dc:subject>
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      <title>vSync Circuits Adds Verific’s Static Elaborator to Product Mix</title>
      <description><![CDATA[Verilog Parser Serves as Front End to New vLinter Rule-Based Design Analysis, Verification Software <pre>Verilog Parser Serves as Front End to New vLinter Rule-Based Design Analysis, Verification Software</pre>]]></description>
      <pubDate>Tue, 03 Dec 2019 16:00 GMT</pubDate>
      <dc:identifier>1955713</dc:identifier>
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      <dc:modified>Tue, 03 Dec 2019 16:00 GMT</dc:modified>
      <dc:subject>Company Announcement</dc:subject>
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      <title>Innergy Systems Powers Up with Verific’s Parser Platform</title>
      <description><![CDATA[SystemVerilog Parser Serves as Front End to Innergy Systems’ Integrated Power Analysis Platform <pre>SystemVerilog Parser Serves as Front End to Innergy Systems’ Integrated Power Analysis Platform</pre>]]></description>
      <pubDate>Wed, 10 Oct 2018 15:00 GMT</pubDate>
      <dc:identifier>1619429</dc:identifier>
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      <dc:publisher>GlobeNewswire Inc.</dc:publisher>
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      <dc:modified>Wed, 10 Oct 2018 15:00 GMT</dc:modified>
      <dc:subject>Company Announcement</dc:subject>
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      <link>https://www.globenewswire.com/news-release/2018/06/13/1521241/0/en/Verific-s-Parser-Platform-License-Secured-by-Empyrean.html</link>
      <title>Verific’s Parser Platform License Secured by Empyrean</title>
      <description><![CDATA[Verilog Parser Functions as Front End to Empyrean’s Library Quality Inspection Software Qualib <pre>Verilog Parser Functions as Front End to Empyrean’s Library Quality Inspection Software Qualib</pre>]]></description>
      <pubDate>Wed, 13 Jun 2018 16:54 GMT</pubDate>
      <dc:identifier>1521241</dc:identifier>
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      <dc:publisher>GlobeNewswire Inc.</dc:publisher>
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      <dc:modified>Wed, 13 Jun 2018 16:54 GMT</dc:modified>
      <dc:subject>Company Announcement</dc:subject>
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      <link>https://www.globenewswire.com/news-release/2018/05/30/1514079/0/en/Verific-Integrates-INVIO-with-Flagship-Parser-Platform.html</link>
      <title>Verific Integrates INVIO with Flagship Parser Platform</title>
      <description><![CDATA[Integration Enables Users to Simplify, Streamline Design Environment <pre>Integration Enables Users to Simplify, Streamline Design Environment</pre>]]></description>
      <pubDate>Wed, 30 May 2018 15:00 GMT</pubDate>
      <dc:identifier>1514079</dc:identifier>
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      <dc:publisher>GlobeNewswire Inc.</dc:publisher>
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      <title>Verific's Parser Platform Selected as Efinix Integrated Design Environment Front End </title>
      <description><![CDATA[<p><em><p>Programmable Product Platform, Technology Innovator Verific Customer Since 2014</p></em></p><p>ALAMEDA, CA--(Marketwired - Oct 11, 2017) - <strong>&#160;</strong><a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation</a> today announced <a rel="nofollow" href="http://www.efinixinc.com/" title="Efinix">Efinix</a>&#8482;, an innovator in programmable product platforms and technology, selected its Verilog Parser Platform and register transfer level (RTL) elaborator to serve as the front end to the Efinity&#8482; Integrated Design Environment (IDE).</p>]]></description>
      <pubDate>Wed, 11 Oct 2017 15:00 GMT</pubDate>
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      <title>Baum Licenses Verific's Parser Platforms </title>
      <description><![CDATA[<p><em><p>SystemVerilog, Verilog Parsers Function as PowerBaum Power Analysis' Front End</p></em></p><p>ALAMEDA, CA--(Marketwired - Sep 26, 2017) -  <a rel="nofollow" href="http://www.baum-ds.com/" title="Baum">Baum</a>, a leader in power analysis solutions, today became the newest licensee of <a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation</a>, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry.</p>]]></description>
      <pubDate>Tue, 26 Sep 2017 15:00 GMT</pubDate>
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      <title>Verific Acquires INVIO Platform from Invionics Software </title>
      <description><![CDATA[<p><em><p>Rapid Application Development Platform will be added to Verific's Parser Platform</p></em></p><p>ALAMEDA, CA--(Marketwired - Jun 12, 2017) -  <a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation</a>, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry, today announced it acquired the INVIO product line from <a rel="nofollow" href="http://www.invionics.com/" title="Invionics Software">Invionics Software</a>. </p>]]></description>
      <pubDate>Mon, 12 Jun 2017 15:00 GMT</pubDate>
      <dc:identifier>1215492</dc:identifier>
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      <dc:publisher>GlobeNewswire Inc.</dc:publisher>
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      <link>https://www.globenewswire.com/news-release/2017/05/23/1215487/0/en/Verific-Signs-Licensing-Agreement-with-Functional-Safety-Solutions-Provider-Austemper-Design-Systems.html</link>
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      <description><![CDATA[<p><em><p>Parser Platform Serves as Front End to Austemper's Functional Safety Tool Suite</p></em></p><p>ALAMEDA, CA--(Marketwired - May 23, 2017) - <a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation</a>, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry, announced a licensing agreement with <a rel="nofollow" href="http://www.austemperdesign.com/" title="Austemper Design Systems">Austemper Design Systems</a>, provider of an end-to-end functional safety solution.</p>]]></description>
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      <pubDate>Tue, 16 May 2017 15:00 GMT</pubDate>
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      <title>Verific to Showcase Three Design Automation Startups With Safety-Features Insertion, Low-Power, Hardware Security Analysis Offerings in Its DAC Booth </title>
      <description><![CDATA[<p><em><p>Reinforces Verific's Innovative Business Model to Jumpstart Design Automation Entrepreneurial Efforts</p></em></p><p>ALAMEDA, CA--(Marketwired - May 24, 2016) -  <a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation</a>, the recognized leader of SystemVerilog, VHDL and UPF parsers, will showcase startup ventures Austemper Design, Innergy Systems and Tortuga Logic in its booth (#538) during the Design Automation Conference (DAC) June 5-9 in Austin, Texas.</p>]]></description>
      <pubDate>Tue, 24 May 2016 15:30 GMT</pubDate>
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      <link>https://www.globenewswire.com/news-release/2016/05/12/1215480/0/en/Two-More-Verific-Licensees-Achieve-Successful-Exits.html</link>
      <title>Two More Verific Licensees Achieve Successful Exits </title>
      <description><![CDATA[<p><em><p>Longtime Customers Yogitech, Rocketick Acquired by Intel, Cadence, Respectively</p></em></p><p>ALAMEDA, CA--(Marketwired - May 12, 2016) -  <a rel="nofollow" href="http://www.verific.com" title="Verific Design Automation">Verific Design Automation</a>, the recognized leader of SystemVerilog, VHDL and UPF parsers, today announced that two of its longtime customers joined a growing list of other customers who have achieved successful exits through acquisitions.</p>]]></description>
      <pubDate>Thu, 12 May 2016 15:00 GMT</pubDate>
      <dc:identifier>1215480</dc:identifier>
      <dc:language>en</dc:language>
      <dc:publisher>GlobeNewswire Inc.</dc:publisher>
      <dc:contributor>Verific Design Automation</dc:contributor>
      <dc:modified>Fri, 01 Dec 2017 01:53 GMT</dc:modified>
    </item>
    <item>
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      <link>https://www.globenewswire.com/news-release/2016/04/19/1215478/0/en/Longtime-Verific-Customer-S2C-Upgrades-to-SystemVerilog.html</link>
      <title>Longtime Verific Customer S2C Upgrades to SystemVerilog </title>
      <description><![CDATA[<p><em><p>SystemVerilog Parser Integrated with Prodigy Prototyping Platform</p></em></p><p>ALAMEDA, CA--(Marketwired - Apr 19, 2016) -  <a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation</a>, the recognized leader of SystemVerilog, VHDL and UPF parsers used throughout the semiconductor industry, announced today <a rel="nofollow" href="http://www.s2cinc.com/" title="S2C, Inc.">S2C, Inc.</a>, a leading provider of FPGA-based rapid prototyping solutions, licensed its SystemVerilog parser.</p>]]></description>
      <pubDate>Tue, 19 Apr 2016 15:00 GMT</pubDate>
      <dc:identifier>1215478</dc:identifier>
      <dc:language>en</dc:language>
      <dc:publisher>GlobeNewswire Inc.</dc:publisher>
      <dc:contributor>Verific Design Automation</dc:contributor>
      <dc:modified>Fri, 01 Dec 2017 01:53 GMT</dc:modified>
    </item>
    <item>
      <guid
        isPermaLink="true">https://www.globenewswire.com/news-release/2016/03/09/1215476/0/en/Verific-Design-Automation-s-Board-Member-Honored-With-DATE-Fellow-Award.html</guid>
      <link>https://www.globenewswire.com/news-release/2016/03/09/1215476/0/en/Verific-Design-Automation-s-Board-Member-Honored-With-DATE-Fellow-Award.html</link>
      <title>Verific Design Automation's Board Member Honored With DATE Fellow Award </title>
      <description><![CDATA[<p><em><p>Yearly Award to Be Presented to Robert Gardner During DATE's Opening Ceremonies</p></em></p><p>ALAMEDA, CA--(Marketwired - Mar 9, 2016) - <strong> </strong>Robert Gardner, longtime member of the <a rel="nofollow" href="http://www.verific.com/" title="Verific Design Automation">Verific Design Automation </a>Board of Directors, will be presented with the yearly DATE Fellow Award by the Design, Automation and Test in Europe (DATE) Conference and Exhibit 2016. </p>]]></description>
      <pubDate>Wed, 09 Mar 2016 15:00 GMT</pubDate>
      <dc:identifier>1215476</dc:identifier>
      <dc:language>en</dc:language>
      <dc:publisher>GlobeNewswire Inc.</dc:publisher>
      <dc:contributor>Verific</dc:contributor>
      <dc:modified>Fri, 01 Dec 2017 01:53 GMT</dc:modified>
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